Modern computing devices utilize a variety of kinds of memory devices to store and access information. Memory devices include the general classes of random access memories (RAM) and read only memories (ROM). These classes further contain static RAM (SRAM), dynamic RAM (DRAM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable PROM (EEPROM), as well as FLASH memory, and the like. Most memory devices employ an internal architecture in the form of an array memory of bit cells, containing plural rows and plural intersecting columns.
A memory cell is placed at each intersecting row and column in the array. Typically, a particular memory cell is accessed by activating its row and then reading or writing the state of its column. Memory sizes are defined by the row and column architecture. For example, a 1024 row by 1024 column memory array defines a memory device having one megabit of memory cells. The array rows are referred to as word lines and the array columns are referred to as bit lines.
The trend in semiconductor memory devices has been toward higher circuit density with higher numbers of bit cells per device, lower operating voltages, and higher access speeds. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels). However, as scaling down device dimensions, sheet resistivity of electrically conductive component of the memory devices (e.g., gates, drain and source regions, emitters of bipolar transistors, local interconnect regions, and interconnect lines) may limit the speed at which memory devices can operate.
To reduce the sheet resistivity of memory devices, a layer of metal silicide can be formed over the surface of electrically conductive component of the memory devices. The resultant silicided components provide the lower resistivity of a metal silicide. While silicides are useful for reducing the sheet resistivity of memory devices, formation of silicides may interfere with the operation of analog circuits by providing undesirable junction leakage. Thus, the requirement of small features with close spacing between adjacent features requires sophisticated manufacturing techniques.